A typical non-volatile memory system, such as flash memory, contains several subsystem circuits which make up the whole memory system. For example, there is the address decode subsystem which takes the memory address bus as input and outputs word lines which select groups of memory cells for writing and reading. In addition, there are input data drivers that interface with the memory array data bit lines for purposes of writing new data into the memory cells. And there are the memory arrays themselves which are made up of memory cells.
For purposes of reading previously stored data out of the memory cells, there is a sense amplifier subsystem. This subsystem senses the data level of bit lines in order to report or read the value of memory cells. The sense amplifier circuitry interfaces with bit lines which are attached to the memory cells and with data output drivers which are the output lines of the memory system.
The power dissipation and speed of sense amplifiers are important design issues, since any improvement to power consumed by sense amplifiers and in the speed of sense amplifiers are magnified several times due to the widespread use of dynamic random access memory.
With prior art sense amplifiers, the voltage at the bit line is precharged to a value that is close to the trigger point of the sense inverter of the sense amplifier (i.e., half way between VDD and VSS). The precharge reduces the bit line charging time and improves read speed. The precharge reduces the bit line charging time and improves read speed. When the input voltage of the inverter is close to the trigger point, the inverter consumes a large “crowbar” current and the output of the inverter does not respond to the input of the data. This consumed power is wasted.
There is also a delay time in the signal between the bit line precharge path and the sense inverter. This leads to overcharges in the precharge level since it takes time to pull the bit line down to the desired sense level, which increases the data access time. That is, larger overcharges lead to longer access times. This situation is illustrated in the timing diagram of FIG. 1 discussed below.
Signal SE is a sense enable control signal. Signal BL represents the bit line voltage. Signal PCH is a bit line precharge control signal. Signal SO is the sense output signal of the sense amplifier. As shown in FIG. 1, when both SE and PCH are high at time t0, bit line charging begins. When the bit line voltage reaches the sense voltage (Vsense) at time t1, PCH goes low. However, the bit line continues to charge for a period after PCH goes low (i.e., until time t2), leading to an overcharge voltage Vopc. Assuming a data “1” state, it takes until time t3 for the bit line voltage to decay to the sense voltage Vsense, at which time the data state (as illustrated by sense output SO) can be detected. The delay between time t1 and t3 increases the data access time.
Finally, the bit line precharge may result in the wrong determination of the bit line precharge level because the charge sharing with the bit line cannot respond as fast as the rising of the voltage on the sensing node. Data errors may occur when attempting to read a “0” out of a memory cell. More specifically, in the case of a long bit line, the capacitance of bit line is large. The bit line cannot respond as fast as the rising of the voltage on the sensing node. The sensing node will reach the precharging level but the bit line has not when the precharging path is turned off. The voltage of the sensing node will then be pulled down to the bit line voltage VBL because of charge sharing, which is lower than the sensing voltage. If the memory cell is weakly-programmed, the cell current is slightly lower than the reference current. The bit line voltage may still be lower than the sensing voltage after the reference sense amplifier is ready. In this case, a read “0” fail occurs.
Improvements in memory cells systems are desired.